This table describes the standard 8051 SFR registers that are implemented in the e8051 core.
Function is similar to standard Dallas 8051, "89C320", unless otherwise noted.
Any non-implemented bit returns 0 when read.

The additional SFRs implemented in the example top-level design, which can be modified or added to by the user in any way, are listed separately below.

#80	P0 (optional)
#81	SP
#82	DPL
#83	DPH
#84	DPL1
#85	DPH1
#86	DPS	d0	data pointer select, 1 bit only
#87	PCON
		d7	SMOD_0	serial port 0 baud rate doubler
		d6	SMOD0	framing error detect enable
#88	TCON		timers 0,1 control and interrupt 0,1 control
#89	TMOD		timers 0,1 mode and gate control
#8A	TL0		timer 0 lsb value
#8B	TL1		timer 1 lsb value
#8C	TH0		timer 0 msb value
#8D	TH1		timer 1 msb value
#8E	CKCON
		d5	T2M timer 2 div 4 mode
		d4	T1M timer 1 div 4 mode
		d3	T0M timer 0 div 4 mode
#8F	-

#90	P1 (optional)
#91	-
#92	-
#93	-
#94	-
#95	-
#96	CKMOD
		d5	T2MH timer 2 div 1 mode (overrides div 4 mode)
		d4	T1MH timer 1 div 1 mode
		d3	T0MH timer 0 div 1 mode
#97	-
#98	SCON0	serial port 0 control
#99	SBUF0	serial port 0 data
#9A	-
#9B	-
#9C	-
#9D	-
#9E	-
#9F	-

#A0	P2 (optional)
#A1	-	
#A2	-	
#A3	-	
#A4	-	
#A5	-	
#A6	-	
#A7	-	
#A8	IE		interrupt enable
#A9	SADDR0 	serial slave address, serial port 0
#AA	SADDR1 	serial slave address, serial port 1
#AB	-	
#AC	-	
#AD	-	
#AE	-	
#AF	-	

#B0	P3 (optional)
#B1	-
#B2	-
#B3	-
#B4	-
#B5	-
#B6	-
#B7	-
#B8	IP		interrupt priority
#B9	SADEN0 	serial slave mask, serial port 0
#BA	SADEN1 	serial slave mask, serial port 1
#BB	-
#BC	-
#BD	-
#BE	-
#BF	-

#C0	SCON1	serial port 1 control
#C1	SBUF1	serial port 1 data
#C2	-
#C3	-
#C4	-
#C5	-
#C6	-
#C7	Reserved address (Timer Functions)
#C8	T2CON	timer 2 control

#C9	T2MOD	timer 2 mode   (d1..d0 only)
		d1	Enables clock output function of the T2 pin (P1.0)
		d0	Timer 2 down count function enable

#CA	RCAP2L	timer 2 capture/load lsb
#CB	RCAP2H	timer 2 capture/load msb
#CC	TL2		timer 2 lsb value
#CD	TH2		timer 2 msb value
#CE	-
#CF	-

#D0	PSW
#D1	-
#D2	-
#D3	-
#D4	-
#D5	-
#D6	-
#D7	-
#D8	WDCON
		d7	SMOD_1
#D9	-
#DA	-
#DB	-
#DC	-
#DD	-
#DE	-
#DF	-

#E0	ACC
#E1	-
#E2	-
#E3	-
#E4	-
#E5	-
#E6	-
#E7	-
#E8	EIE		extended interrupt enables register
#E9	E2IE	extended interrupt enables register 2
#EA	-
#EB	-
#EC	-
#ED	-
#EE	-
#EF	-

#F0	B reg
#F1	-
#F2	-
#F3	-
#F4	-
#F5	-
#F6	-
#F7	-
#F8	EIP		extended interrupt priority register
#F9	E2IP	extended interrupt priority register 2
#FA	-
#FB	-
#FC	-
#FD	-
#FE	-
#FF	-



Optional SFR's supplied in the example top level design, 
these can be altered or added to in any way by the user:-


#A1 Address Map control Reg
		d7	BOOT ROM ON in code memory space	- default ON
		d6	CODE READ/WRITE redirects RD/WR to soft code memory - default ON
		d5	JUMP VECTOR ON powerup auto jump to bootrom code - default ON

		d0	Force non-maskable Power Fail Interrupt (for test purposes) - default OFF
			
#A2 External Bus Mode Select
		d7	EARLY PSEN external psen strobe starts at earliest possible 
				time, without waiting for stable address - default OFF
		d6	EARLY MRD external RD strobe starts at earliest possible 
				time, without waiting for stable address - default OFF

#A3 External Setup Stretch
		Number of clock cycles to extend external bus-signal setup/hold times

#A4 External Strobe Stretch
		Number of clock cycles to extend external PSEN, RD and WR times

#A5 External Recover Stretch
		Number of clock cycles to extend recovery from external PSEN and RD 
		operations